Overview 14 matches · 0 in Waratek scope · 0 protected · 2 exploited · 0 CISA KEV · 4 public PoC · 4 EPSS ≥ 0.5
14matches
0in Waratek scope0.0%
0protected0.0%
2exploited14.3%
0CISA KEV0.0%
4public PoC28.6%
4EPSS ≥ 0.528.6%
Protected by Waratek
0
0.0%
Rule in development
0
0.0%
Mitigation candidate
0
0.0%
No exploit published
0
0.0%
Outside Waratek scope
3
21.4%
Not applicable
11
78.6%
Withdrawn CVE
0
0.0%
blocked by ARMR today
0
0.0%
partly blocked
0
0.0%
not blocked
14
100.0%
not established
0
0.0%
unrecorded
0
0.0%
split by
peak 7 / year
20187
Outside Waratek scope3
Not applicable4
Medium7
not blocked7
Exploited2
Working exploit published1
Proof of concept only1
No public exploit3
20190
20201
Not applicable1
Medium1
not blocked1
No public exploit1
20212
Not applicable2
Medium2
not blocked2
No public exploit2
20222
Not applicable2
Medium2
not blocked2
No public exploit2
20231
Not applicable1
Medium1
not blocked1
No public exploit1
20240
20251
Not applicable1
Medium1
not blocked1
No public exploit1
20182019202020212022202320242025
| CVE | Severity | Published▾ | Status | Exploitation | Description |
|---|---|---|---|---|---|
| CVE-2024-10929 | Medium | 2025-01-22 | Not applicable | No public exploit | In certain circumstances, an issue in Arm Cortex-A57, Cortex-A72 (revisions before r1p0), Cortex-A73 and Cortex-A75 may allow an adversary to gain a weak form of control over the victim's branch history. |
| CVE-2023-34320 | Medium | 2023-12-08 | Not applicable | No public exploit | Cortex-A77 cores (r0p0 and r1p0) are affected by erratum 1508412 where software, under certain circumstances, could deadlock a core due to the execution of either a load to device or non-cacheable memory, and either a store exclusive or register read of the Physical Address Register (PAR_EL1) in close proximity. |
| CVE-2022-23960 | Medium | 2022-03-13 | Not applicable | No public exploit | Certain Arm Cortex and Neoverse processors through 2022-03-08 do not properly restrict cache speculation, aka Spectre-BHB. An attacker can leverage the shared branch history in the Branch History Buffer (BHB) to influence mispredicted branches. Then, cache allocation can allow the attacker to obtain sensitive information. |
| CVE-2022-25368 | Medium | 2022-03-10 | Not applicable | No public exploit | Spectre BHB is a variant of Spectre-v2 in which malicious code uses the shared branch history (stored in the CPU BHB) to influence mispredicted branches in the victim's hardware context. Speculation caused by these mispredicted branches can then potentially be used to cause cache allocation, which can then be used to infer information that should be protected. |
| CVE-2021-26314 | Medium | 2021-06-09 | Not applicable | No public exploit | Potential floating point value injection in all supported CPU products, in conjunction with software vulnerabilities relating to speculative execution with incorrect floating point results, may cause the use of incorrect data from FPVI and may result in data leakage. |
| CVE-2021-26313 | Medium | 2021-06-09 | Not applicable | No public exploit | Potential speculative code store bypass in all supported CPU products, in conjunction with software vulnerabilities relating to speculative execution of overwritten instructions, may cause an incorrect speculation and could result in data leakage. |
| CVE-2020-13844 | Medium | 2020-06-08 | Not applicable | No public exploit | Arm Armv8-A core implementations utilizing speculative execution past unconditional changes in control flow may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis, aka "straight-line speculation." |
| CVE-2018-3693 | Medium | 2018-07-10 | Not applicable | No public exploit | Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a speculative buffer overflow and side-channel analysis. |
| CVE-2018-3640 | Medium | 2018-05-22 | Not applicable | No public exploit | Systems with microprocessors utilizing speculative execution and that perform speculative reads of system registers may allow unauthorized disclosure of system parameters to an attacker with local user access via a side-channel analysis, aka Rogue System Register Read (RSRE), Variant 3a. |
| CVE-2018-3639 | Medium | 2018-05-22 | Outside Waratek scope | Exploited | Systems with microprocessors utilizing speculative execution and speculative execution of memory reads before the addresses of all prior memory writes are known may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis, aka Speculative Store Bypass (SSB), Variant 4. |
| CVE-2018-9056 | Medium | 2018-03-27 | Not applicable | No public exploit | Systems with microprocessors utilizing speculative execution may allow unauthorized disclosure of information to an attacker with local user access via a side-channel attack on the directional branch predictor, as demonstrated by a pattern history table (PHT), aka BranchScope. |
| CVE-2017-5754 | Medium | 2018-01-04 | Not applicable | Proof of concept only | Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis of the data cache. |
| CVE-2017-5753 | Medium | 2018-01-04 | Outside Waratek scope | Exploited | Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis. |
| CVE-2017-5715 | Medium | 2018-01-04 | Outside Waratek scope | Working exploit published | Systems with microprocessors utilizing speculative execution and indirect branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis. |