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Including CVEs outside Waratek scope✕Product cortex-a✕
Overview 13 matches · 0 in Waratek scope · 0 protected · 0 exploited · 0 CISA KEV · 0 public PoC · 0 EPSS ≥ 0.5
13matches 0in Waratek scope0.0% 0protected0.0% 0exploited0.0% 0CISA KEV0.0% 0public PoC0.0% 0EPSS ≥ 0.50.0%
Protected by Waratek 0 0.0% Rule in development 0 0.0% Mitigation candidate 0 0.0% No exploit published 0 0.0% Outside Waratek scope 0 0.0% Not applicable 13 100.0% Withdrawn CVE 0 0.0%
Critical 1 7.7% High 2 15.4% Medium 10 76.9% Low 0 0.0% None 0 0.0% Unknown 0 0.0%
blocked by ARMR today 0 0.0% partly blocked 0 0.0% not blocked 13 100.0% not established 0 0.0% unrecorded 0 0.0%
Exploited 0 0.0% Working exploit published 0 0.0% Proof of concept only 0 0.0% Forecast only 0 0.0% No public exploit 13 100.0%
split by peak 3 / year
Not applicable: 13 Medium: 10High: 2Critical: 1 not blocked: 13 No public exploit: 13
20183 Not applicable3 Medium3 not blocked3 No public exploit3 20190 20201 Not applicable1 Medium1 not blocked1 No public exploit1 20212 Not applicable2 Medium2 not blocked2 No public exploit2 20222 Not applicable2 Medium2 not blocked2 No public exploit2 20232 Not applicable2 High1 Medium1 not blocked2 No public exploit2 20241 Not applicable1 Critical1 not blocked1 No public exploit1 20251 Not applicable1 Medium1 not blocked1 No public exploit1 20261 Not applicable1 High1 not blocked1 No public exploit1
201820192020202120222023202420252026
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CVE Severity Published▾ Status Exploitation Description
CVE-2025-0647 High 2026-01-14 Not applicable No public exploit In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
CVE-2024-10929 Medium 2025-01-22 Not applicable No public exploit In certain circumstances, an issue in Arm Cortex-A57, Cortex-A72 (revisions before r1p0), Cortex-A73 and Cortex-A75 may allow an adversary to gain a weak form of control over the victim's branch history.
CVE-2024-5660 Critical 2024-12-10 Not applicable No public exploit Use of Hardware Page Aggregation (HPA) and Stage-1 and/or Stage-2 translation on Cortex-A77, Cortex-A78, Cortex-A78C, Cortex-A78AE, Cortex-A710, Cortex-X1, Cortex-X1C, Cortex-X2, Cortex-X3, Cortex-X4, Cortex-X925, Neoverse V1, Neoverse V2, Neoverse V3, Neoverse V3AE, Neoverse N2 may permit bypass of Stage-2 translation and/or GPT protection.
CVE-2023-34320 Medium 2023-12-08 Not applicable No public exploit Cortex-A77 cores (r0p0 and r1p0) are affected by erratum 1508412 where software, under certain circumstances, could deadlock a core due to the execution of either a load to device or non-cacheable memory, and either a store exclusive or register read of the Physical Address Register (PAR_EL1) in close proximity.
CVE-2022-48251 High 2023-01-10 Not applicable No public exploit The AES instructions on the ARMv8 platform do not have an algorithm that is "intrinsically resistant" to side-channel attacks. NOTE: the vendor reportedly offers the position "while power side channel attacks ... are possible, they are not directly caused by or related to the Arm architecture."
CVE-2022-23960 Medium 2022-03-13 Not applicable No public exploit Certain Arm Cortex and Neoverse processors through 2022-03-08 do not properly restrict cache speculation, aka Spectre-BHB. An attacker can leverage the shared branch history in the Branch History Buffer (BHB) to influence mispredicted branches. Then, cache allocation can allow the attacker to obtain sensitive information.
CVE-2022-25368 Medium 2022-03-10 Not applicable No public exploit Spectre BHB is a variant of Spectre-v2 in which malicious code uses the shared branch history (stored in the CPU BHB) to influence mispredicted branches in the victim's hardware context. Speculation caused by these mispredicted branches can then potentially be used to cause cache allocation, which can then be used to infer information that should be protected.
CVE-2021-26314 Medium 2021-06-09 Not applicable No public exploit Potential floating point value injection in all supported CPU products, in conjunction with software vulnerabilities relating to speculative execution with incorrect floating point results, may cause the use of incorrect data from FPVI and may result in data leakage.
CVE-2021-26313 Medium 2021-06-09 Not applicable No public exploit Potential speculative code store bypass in all supported CPU products, in conjunction with software vulnerabilities relating to speculative execution of overwritten instructions, may cause an incorrect speculation and could result in data leakage.
CVE-2020-13844 Medium 2020-06-08 Not applicable No public exploit Arm Armv8-A core implementations utilizing speculative execution past unconditional changes in control flow may allow unauthorized disclosure of information to an attacker with local user access via a side-channel analysis, aka "straight-line speculation."
CVE-2018-3693 Medium 2018-07-10 Not applicable No public exploit Systems with microprocessors utilizing speculative execution and branch prediction may allow unauthorized disclosure of information to an attacker with local user access via a speculative buffer overflow and side-channel analysis.
CVE-2018-3640 Medium 2018-05-22 Not applicable No public exploit Systems with microprocessors utilizing speculative execution and that perform speculative reads of system registers may allow unauthorized disclosure of system parameters to an attacker with local user access via a side-channel analysis, aka Rogue System Register Read (RSRE), Variant 3a.
CVE-2018-9056 Medium 2018-03-27 Not applicable No public exploit Systems with microprocessors utilizing speculative execution may allow unauthorized disclosure of information to an attacker with local user access via a side-channel attack on the directional branch predictor, as demonstrated by a pattern history table (PHT), aka BranchScope.